This invention relates to a method of manufacturing a semiconductor device, and more particularly to a manufacturing technique of changing an outputting manner at an output port at the time of writing information into each of elements which constitute a mask ROM (Read Only Memory).
In order to shorten the TAT (Turn Around Time) of a mask ROM, various techniques of ion-implanting for writing information (which is also referred to as “program write” or “ROM write”) after an Al wiring has been formed are known. Referring to FIGS. 6A to 6D, an explanation will be given of a conventional manufacturing technique.
Step 1: As seen from FIG. 6A, using the technique of thermal oxidation or CVD, a pad oxide film 52 of a silicon oxide film having a thickness of 25 nm is formed on a P-type semiconductor substrate 51. The pad oxide film 52 is formed to protect the surface of the semiconductor substrate 51.
Next, a silicon nitride film 53 which is an oxidation-resistant film is formed on the entire surface. Thereafter, lengthy stripes of openings 53a for forming element isolation films 54 are formed in the silicon nitride film 53 in a direction perpendicular to a paper face of this drawing.
Step 2: As seen from FIG. 6B, using the technique of LOCOS with the silicon nitride film as a mask, the semiconductor substrate 51 is oxidized to form element isolation films 54. At this time, oxide regions invades between the semiconductor substrate 51 and silicon nitride film 53 so that a bird's beaks 54a are formed. Next, the silicon nitride film 53 and pad oxide film 52 are removed, and using the technique of thermal oxidation, a gate insulating film 55 having a thickness of 14 nm to 17 nm is formed. Using the technique of CVD, a poly-Si film having a thickness of 350 nm is formed, and phosphorus is doped to form an N-type conductive film 56.
Step 3: As seen from FIG. 6C, the conductive film 56 is etched in lengthy strips in a direction orthogonal to the element isolation films 54 (it should be noted that the etched region, which is in parallel to the paper face, is not illustrated) to form gate electrodes 56a which serve as word lines. Using the gate electrodes 56a as a mask, P-type impurities such as boron are ion-implanted to form a source region and a drain region (which are not illustrated since they are formed below both ends of the gate electrode in a direction perpendicular to the paper face).
Through the process described above, memory cell transistors arranged in a matrix shape are formed. An interlayer insulating film 57 having a thickness of 500 nm of a silicon oxide film is formed on the entire surface. Al wirings 58 in lengthy strips, which serve as bit lines, are formed above the element isolation films 54, respectively in a direction perpendicular to the paper face. Until this step, the manufacturing process can be carried out irrespectively of what program should be written in the memory cell transistors. For this reason, the wafers can be previously manufactured. In this case, a silicon oxide film 59 serving as a protection film is formed on the entire surface.
Step 4: At the time when a program to be written is determined on receipt of a request from a customer, as seen from FIG. 6D, a photoresist 60 having openings 60a for writing a program for a mask ROM is formed. P type impurities such as boron are ion-implanted in the semiconductor substrate 51 immediately beneath the gate electrodes 56a from the openings 60a so that predetermined memory cell transistors are depleted. Thus, the threshold voltages of the memory cell transistors are lowered so that a ROM data is written.
Now, in changing the mask ROM, the outputting manner of an output port for each user must be changed into either an open drain output or an inverter output.
In this case, as the step of changing the outputting manner at the output port, the operation of depleting a P-channel MOS transistor was performed by implanting boron ions before a gate electrode is formed.
Where the changing the outputting manner at an output port is performed by the step of ion-implanting before the gate electrode is formed, this step is a very early step. Therefore, the advantage of performing the step of writing the ROM data as a later step is lost.
Further, the opening of the photoresist film which is used when the switch for changing the outputting manner at the output port is formed is smaller than the opening for writing the ROM, and the openings for forming switches are formed adjacently to each other so as to correspond to a plurality of pads 32 (FIG. 4A).
However, the ROM 29 and PD switches 30 are formed in a certain limited area of the substrate (chip) 1 (For example, although not illustrated, an SRAM region and logic unit region are formed in a wider area than the ROM region). Therefore, no opening is formed in the other relatively wide region than the opening for write of the ROM and openings for the PD switches so that the proportion of the area of the photoresist film is large.
Owing to the tension from the photoresist film with no opening, which occupies a wide region on the chip, the sectional shape of the openings are not substantially vertical but tilt. Thus, the diameter of each of the openings at its upper part is increased.
Therefore, if the interlayer insulating film is etched as it is, the etching proceeds in reflection of the above tilting. As a result, an etched shape leaves the interlayer insulating film on the transistor in which the write for the ROM and the outputting manner of the output port should be switched. Particularly, this greatly influences the openings for the switches each of which has a smaller than that of the opening for write of the ROM and which are adjacent to each other so as to correspond to the plurality of pads 32.
As a result, as the case may be, impurities are not sufficiently implanted in the channel region of the transistor for which the write of ROM is to be carried out and to be switched, thus defective write and switching occurs.